Deep power saving by disabling clock distribution without separate clock distribution for power management logic

ABSTRACT

An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

CROSS-REFERENCED APPLICATIONS

This application relates to co-pending U.S. patent applications entitled “A METHOD TO GATE OFF PLLS IN A DEEP POWER SAVING STATE WITHOUT SEPARATE CLOCK DISTRIBUTION FOR POWER MANAGEMENT LOGIC” (Docket No. AUS920030695US1), filed concurrently herewith.

FIELD OF THE INVENTION

The present invention relates generally to clocking distribution, and more particularly, to clock distribution gating in a microprocessor.

DESCRIPTION OF THE RELATED ART

In conventional microprocessors, power consumption control has been evolving. Within microprocessors, there are three types of phenomenon that result in power consumption: direct current (DC) leakage, the clock, and alternating current (AC) usage. DC leakage is a product of the devices themselves losing charge when the system is powered. For example, thin film capacitors within a microprocessor will lose charge due to a leakage current. The clocking distribution system, mesh, or tree consumes power due the constant toggling that occurs, and the AC usage is the switching power required for active switching of the logic in the microprocessor.

Because of temperature requirements, limitations of power sources, limitations of the device, as well as other factors, there is a constant strived for a reduction in the power consumption of the microprocessors. These power reduction solutions have taken many different forms. For example, disengaging entire sections of logic on the microprocessor when not in use for extended periods of time is often employed. Also, improving the quality with which the microprocessors are manufactured is employed.

However, several techniques have been employed to reduce power consumption by the clocking distribution system. The clocking distribution system can often consume 15% or more of the total chip power. Therefore, it would be desirable to gate off the clocking distribution when the processor is in a deep power saving mode. However, pervasive logic controlling the gating of the clock distribution requires a clock to operate. Some conventional solutions utilize a separate clock for the control logic so that the control logic functions while the main clock distribution is gated off.

Having a separate clock for the control logic, however, has several drawbacks. Designing such a clocking system is difficult, requiring many man-hours. Control logic is limited to the separate clock distribution physical boundary, making integration difficult. Additionally, the separate clock distribution may be asynchronous to the main clock mesh, creating difficulty for signals crossing the synchronous-asynchronous boundary.

Therefore, there is a need for a method and/or apparatus for reducing power consumption by a clock distribution system the addresses at least some of the problems associated with conventional solutions.

SUMMARY OF THE INVENTION

The present invention provides a method and computer program for disabling clock distribution while a processor is in power save mode. A plurality of power mode signals is generated. Then, based on the plurality of power mode signals, the clock distribution to the processor is disrupted.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram chip that employs a clock gating system; and

FIG. 2 is a timing diagram depicting the operation of the clock gating system.

DETAILED DESCRIPTION

In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electromagnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.

It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combinations thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.

Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates chip that employs a clock gating system. The chip 100 comprises a chip IO 102, a phased locked loop (PLL), a multiplexer (mux) 106, an AND gate 124, and a system 108.

For the chip 100 to function, the PLL 110 can apply one of several frequency clocking signals to the system 108. The PLL 110 receives a reference clock signal (REF_CLK) through the communication channel 120 and generates a plurality of output clocking signals FREQ(0) to FREQ(n). The PLL 110 transmits the clocking signals to the mux 106 through the communication channels 122 and 126. However, for each clocking frequency generated by the PLL 110, there is a designated communication channel for each frequency, but only two communication channels are depicted for the purposes of illustration. Then one of the frequencies output from the PLL 110 is selected by virtue of the frequency select (FREQ_SELLS) signal into the mux 106 through the communication channel 118. The mux can then output a clocking signal (CLK) to the system 108 through the communication channel.128.

The CLK, however, can be gated off due to the outputs from the Chip IO 102 and the pervasive logic 104 of the system 108. The Chip IO 102 outputs a power same mode acknowledge (PSM_ACK) to the AND gate 124 through the communication channel 112. The PSAM_ACK is typically related through the Chip IO 102 from an external device. Additionally, the pervasive logic 104 outputs a clock enable signal (CLK_EN) signal to the AND gate 124 through the communication channel 114. Under circumstances when PSM_ACK and CLK_EN are logic high, then a disable signal is transmitted to the mux 106 through the communication channel 116. The disable signal disables the mux 106 so that no clocking signal is transmitted to the system 108.

The operation of the system, however, can be illustrated through a timing diagram. Referring to FIG. 2 of the drawings, the reference numeral 200 generally designates a timing diagram depicting the operation of the clock gating system.

During normal operation, CLK toggles as normal. At ti, however, the CLK is disabled. Prior to t₁, PSM_ACK transitions to logic high. Due to the use of the AND gate 124, though, the PSM_ACK signal is not determinative. It is not until t₁, when CLK_EN transitions to logic high, that CLK is disabled. Then, at t₂, PSM_ACK transitions back to logic low, causing CLK to be enabled once again.

Specifically, the operation of the clock gating system is employed during a power save mode. Within this mode the clock distribution is shut down. Then, reactivation occurs as a result of an external handshake signal(s) that “wakes up” the processor. These handshake signals are level sensitive signals that are monitored while the processor is in power saving mode. Within the configuration of the chip 100 of FIG. 1, the handshake signals are monitored with static (combinational) logic instead of a separate clock distribution. Therefore, clock distribution that is not utilized can be disabled without having to employ a separate clock distribution.

It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.

Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention. 

1. An apparatus for disabling clock distribution while a processor is in power save mode, comprising: means for toggling the clock distribution to the processor; means for toggling signals external to the processor to activate the processor from the power save mode; and means for using combinational logic to monitor the signals external to the processor.
 2. The apparatus of claim 1, wherein the combinational logic further comprises a multiplexer (mux).
 3. An apparatus for disabling clock distribution while a processor is in power save mode, comprising: at least one logic gate for receiving a plurality of enable signals; and combinational logic that is at least configured to relay the output of the clock distribution based on the output of the at least one logic gate.
 4. The apparatus of claim 3, wherein the clock distribution further comprises a Phased Locked Loop (PLLs) for generating a plurality of clocking signals.
 5. The apparatus of claim 3, wherein the at least one logic gate further comprises an AND gate.
 6. The apparatus of claim 5, wherein the plurality of enable signals further comprises: a power save mode acknowledge (PSM_ACK) signal generated by an external device; and a clock enable (CLK_EN) signal generated by the processor.
 7. The apparatus of claim 3, wherein the combinational logic further comprises a mux.
 8. A method for disabling clock distribution while a processor is in power save mode, comprising: toggling the clock distribution to the processor; toggling signals external to the processor to activate the processor from the power save mode; and using combinational logic to monitor the signals external to the processor.
 9. The method of claim 8, wherein the step of using combinational logic further comprises ANDing the signals external to the processor and a signal from the processor.
 10. A method for disabling clock distribution while a processor is in power save mode, comprising: generating a plurality of power mode signals; and disrupting the clock distribution to the processor based on the plurality of power mode signals.
 11. The method of claim 10, wherein the step of generating further comprises: receiving a PSM_ACK signal form an external device; and generating a CLK_EN signal by the processor.
 12. The method of claim 10, wherein the method further comprises logically combining the plurality of power mode signals to generate a disrupt signal.
 13. The method of claim 12, wherein the step of disrupting further comprises employing combinational logic to disrupt the clock distribution.
 14. The method of claim 12, wherein the step of logically combining further comprises ANDing the plurality of power mode signals.
 15. A computer program product for disabling clock distribution while a processor is in power save mode, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for generating a plurality of power mode signals; and computer code for disrupting the clock distribution to the processor based on the plurality of power mode signals.
 16. The computer program product of claim 15, wherein the computer code for generating further comprises: computer code for receiving a PSM_ACK signal form an external device; and computer code for generating a CLK_EN signal by the processor.
 17. The computer program product of claim 15, wherein the computer program product further comprises computer code for logically combining the plurality of power mode signals to generate a disrupt signal.
 18. The computer program product of claim 17, wherein the computer code for disrupting further comprises employing combinational logic to disrupt the clock distribution.
 19. The computer program product of claim 17, wherein the computer code for logically combining further comprises ANDing the plurality of power mode signals. 